* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.

Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0 CKE0 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 DM0 to DM8 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0 /RESET Par_In* 2 2 www.DataSheet4U.com Function Address input Row.

EBE10AD4AGFA

EBE10AD4AJFA

EBE10EE8ACFA

EBE10EE8ACWA

EBE10RD4ABFA

EBE10RD4AEFA

EBE10RD4AEFA-6

EBE10RD4AGFA

EBE10RD4AJFA

EBE10UE8ACFA

EBE10UE8ACWA

EBE10UE8ACWB

EBE10UE8AEFA